HP Moonshot: dream machine or déjà vu?

You have probably already seen news about ARM in servers, Calxeda forming partnership with HP and delivering first prototypes of ARM-based server board/case/infrastructure in HP Moonshot program/machine. To be honest this machine looks really nice and I’m happy to see HP doing some work into this domain.

From the Haskell point of view, it would be extremely exciting if such beast might be programmed using Data Parallel Haskell.

But wait, isn’t this just déjà vu? Where have I seen something like that already? …. indeed! *Lisp! CM-x! Mr. Hillis and his team still rocks since *List was already there while DPH backend for Moonshot is still to be written…more than 25 years later after the *Lisp 🙂

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ARMv8: few details.

It looks like few details about ARMv8 are starting to appear on the network. The root of this is presentation and videos about ARMv8 made by Richard Grisenthwaite and which are now linked from the ARM ISAs page. Please just scroll down and select ARMv8 Resources tab.
Anyway, I’d like to list a few details also here especially focused on details which affect user-land application writer. Small table should do the job I hope. Please note that with ARMv8, ARM started to name various ISAs as A32, which is classical ARM, T32, which is Thumb2 and A64 which is new ISA for ARM 64bit computing. So far ARMv7’s and ARMv8’s A32 and T32 ISAs looks similar.

ARMv7 ARMv8
32 bit ISAs A32, T32 A32, T32
64 bit ISAs A64
Number of GPs 13* 13* (A32, T32), 31** (A64)
ISNs encoding length (bits) 16-32 (T32), 32 (A32) 16-32 (T32), 32 (A32), 32 (A64)
NEON 64 bit regs 32 32
NEON 128 bit regs 16 32
Crypto ISNs (using NEON regs) AES, SHA-1, SHA-256

*: I count only R0-R12
**: PC and SP are no longer considered GPs

So as you can see, we get nearly twice the general purpose registers, twice the number of 128 bit registers in NEON and we also get some additional instructions to support some common cryptography operations. Besides this A64 also provides new load-acquire/store-release instructions to better support ARM weak-memory model in higher level programming languages.

Well, so from the point of view of GHC this might indeed be fun. The only pity is that we still depend on LLVM to come with A64 support first and then we’ll be able to use it in GHC.

New hardware: ThinkPad Tablet

My new target hardware for the GHC port arrived a week ago. It is a brand new ThinkPad Tablet which contains NVidia Tegra2 CPU, 1GB RAM and 64GB FLASH. It is also equipped with 3G modem which I’m not using as the price of 3G internet in The Czech Republic is prohibitive (one of the highest in EU!) and I really don’t like to support those greedy carriers.

ThinkPad Tablet accompanied by Tablet's pen and alto recorder showing web page of the Real World Haskell book.


Anyway, this is my first tablet ever and also first tablet with real pen input! I’ve been always dreaming about really personal computer which would work like an “inteligent” diary. This one does have ability to fulfill this dream — at least on the paper. Well, well, everything does have its own set of bugs and ThinkPad Tablet is not different, but I still like it a lot. Especially those application with builtin pen capability, e.g. MyScript Notes. If you don’t know the application, I highly recommend you to see this video to get some idea what’s this about.

Now, what about to have a GHCi editor with pen input? Would be nice, wouldn’t it? 🙂

LLVM patch is merged for inclusion in LLVM 3.0 release

Good news for those shy to patch LLVM source code and build from scratch. 🙂 The patch which adds GHC calling convention for ARM platform is merged for inclusion in LLVM 3.0 release. This is mainly due to David Terei persistence and constant push on Apple engineering to get it in since I’ve submitted the patch for inclusion just last day and was not able to answer all the questions arising from it. David not only replied with all needed information, but also kept emailing LLVM 3.0 release engineer and asking for inclusion. Thanks David!