It looks like few details about ARMv8 are starting to appear on the network. The root of this is presentation and videos about ARMv8 made by Richard Grisenthwaite and which are now linked from the ARM ISAs page. Please just scroll down and select ARMv8 Resources tab.
Anyway, I’d like to list a few details also here especially focused on details which affect user-land application writer. Small table should do the job I hope. Please note that with ARMv8, ARM started to name various ISAs as A32, which is classical ARM, T32, which is Thumb2 and A64 which is new ISA for ARM 64bit computing. So far ARMv7’s and ARMv8’s A32 and T32 ISAs looks similar.
|32 bit ISAs||A32, T32||A32, T32|
|64 bit ISAs||—||A64|
|Number of GPs||13*||13* (A32, T32), 31** (A64)|
|ISNs encoding length (bits)||16-32 (T32), 32 (A32)||16-32 (T32), 32 (A32), 32 (A64)|
|NEON 64 bit regs||32||32|
|NEON 128 bit regs||16||32|
|Crypto ISNs (using NEON regs)||—||AES, SHA-1, SHA-256|
*: I count only R0-R12
**: PC and SP are no longer considered GPs
So as you can see, we get nearly twice the general purpose registers, twice the number of 128 bit registers in NEON and we also get some additional instructions to support some common cryptography operations. Besides this A64 also provides new load-acquire/store-release instructions to better support ARM weak-memory model in higher level programming languages.
Well, so from the point of view of GHC this might indeed be fun. The only pity is that we still depend on LLVM to come with A64 support first and then we’ll be able to use it in GHC.